The present invention relates to an electronic device and, more particularly, to communications within an integrated circuit in an electronic device or between such integrated circuits and to techniques for increasing the operation speed and reducing the area and power consumption by using a transmission line.
A conventional method for high-speed communications within an integrated circuit including a semiconductor in an electronic device or between such integrated circuits includes the use of a transmission line between the transmitter circuit and the receiver circuit. The transmission line includes a device element, with which it is possible to obtain the same impedance value as the characteristic impedance of the line being a conductor. With a transmission line of a single line scheme, the device element is connected between the signal-carrying conductor line and the return path in the vicinity of the receiver circuit. With a transmission line of a differential transmission system, the device element is connected between two signal-carrying conductor lines.
With such a method, the coefficient of reflection of the signal propagating along the conductor line is suppressed to zero as much as possible, so that a reliable signal voltage waveform is generated near, and received by, the receiver circuit. One such technique is described in Yuzo Usui, “All About Distributed Parameter Circuit For Board Designers”, Chapters 6 and 9 (Non-Patent Document 1).
With such a transmission line, actual signals to be transmitted do not always have the same frequency, and the signal reflection coefficient cannot be made zero due to the inter-symbol interference (ISI).
Conventional countermeasures against the problem include the duobinary signaling technique described in “12 Gb/s Duobinary Signaling with ×2 Oversampled Edge Equalization”, IEEE International Solid-State Circuits Conference 2005, Session 3.6 (Non-Patent Document 2), the preemphasis technique described in “A 3-Gb/s/ch Transceiver for 10-mm Uninterrupted RC-Limited Global On-Chip Interconnects”, IEEE Journal of Solid-State Circuits, vol. 41, no. 1, p. 297, January 2006 (Non-Patent Document 3), the return zero (RZ) technique described in “Pulsed Current-Mode Signaling for Nearly Speed-of-Light Intrachip Communication”, IEEE Journal of Solid-State Circuits, vol. 41, no. 4, p. 772, April 2006 (Non-Patent Document 4), and the equalizer technique described in “A Fully Integrated 10 Gbp/s Receiver with Adaptive Optical Dispersion Equalizer in 0.13 μm CMOS”, IEEE Journal of Solid-State Circuits, vol. 42, no. 4, p. 872, April 2007 (Non-Patent Document 5) and “A 5 mW 6 Gbp/s Quarter-Rate Sampling Receiver with a 2-Tap DFE Using Soft Decisions”, IEEE Journal of Solid-State Circuits, vol. 42, no. 4, p. 881, April 2007 (Non-Patent Document 6).
With the configurations of Non-Patent Documents 2 to 6, however, extra circuits need to be added to the transmitter circuit and the receiver circuit, thereby increasing the area and power consumption of the transmitter circuit and those of the receiver circuit.
The signal reflection coefficient is prevented from becoming zero also by, for example, manufacturing variations of the device element, which is placed in the vicinity of the receiver circuit of the transmission line, variations in the device temperature thereof, and variations in the applied voltage value thereof. In order to solve this problem, Japanese Laid-Open Patent Publication No. 7-297678 (Patent Document 1) discloses a conventional technique of realizing, by means of a MOS resistive element (hereinafter referred to as a “terminating resistor”), an impedance value such that the signal waveform is unlikely to be reflected in the vicinity of the receiving terminal.
With this method, the value of the terminating resistor can be adjusted by a CMOS circuit technique. Specifically, this is a feedback system where an equal amount of current is conducted for a reference resistor value and for a replica CMOS terminating resistor value to make a comparison between the voltage values each obtained by multiplying the resistance value by the current value, based on which the gate voltage value of the replica CMOS is adjusted so that the reference resistor value and the replica CMOS terminating resistor value are equal to each other. The gate voltage value of the replica CMOS is applied also to the gate of the CMOS terminating resistor circuit so that the terminating resistor eventually has a resistance value equal to the value of the reference resistor.
With the method of Patent Document 1, however, the reference resistor needs to be placed outside the semiconductor integrated circuit. If the reference resistor is provided inside the semiconductor integrated circuit, the terminating resistor value will then vary due to process variations and temperature variations, whereby it will not be possible to accurately achieve the impedance match. Then, the signal voltage waveform in the vicinity of the receiver circuit has disturbed phase, resulting in unreliable data being received.